The invention relates to a method and apparatus for testing structures in semiconductor wafers.
Typically, during the production of semiconductor chips and other electronic devices, testing is carried out to ensure proper functioning of the chips or other devices. In some cases, only particular portions of the chips or other devices may be tested. For example, various structures formed in a semiconductor chip may be tested to ensure proper electrical functioning.
Often, during testing, a probe contacts a structure formed on a semiconductor wafer. Electrical current may then flow through the probe into the structure. As the testing device contacts the structure on the semiconductor wafers, it may actually generate defects in the structures. For example, test probes may impact with a force sufficient to indent and/or scratch test pads on the semiconductor wafers. Also, depending upon the force of the probe tip, insulator cracking may occur. These problems are particularly bad when testing uncapped copper and aluminum structures.
Damage to a test pad or other structure on a semiconductor wafer as a result of contact by a testing probe is often severe enough to cause yield losses at subsequent levels of build. Approaches for addressing damage to structures in semiconductor wafers may involve treating the defects generated by the testing process rather than preventing the defects. According to one method to address test probe related defects, post-test brush cleaning is utilized. According to another method, post-test mild kiss polishing is utilized. According to a third method, the decision is not to test at the intermediate levels, but to defer testing to the final metal level.
Each of the above-described methods for addressing test probe generated defects has associated penalties. Along these lines, deferring testing until the final metal level may result in missing defects that could have permitted the product wafer to be discarded prior to further processing. Alternatively, both cleaning and polishing may result in further damage to the structures that have been damaged during testing as well as to create defects in previously pristine surrounding structures. At a minimum, time and money must be expended to address the above-described problems. Also, the defects can result in waste through their inclusion in the products being tested.
The present invention provides methods and apparatuses for reducing test related defects. In accordance with these and other objects and advantages, the present invention provides an apparatus for testing structures in semiconductor wafers. The apparatus includes at least one test probe. The apparatus also includes at least one tool for measuring and controlling deceleration of the at least one test probe as it approaches the surface of a structure in the semiconductor wafer.
The present invention also provides a method of testing structures in semiconductor wafers. The method includes directing at least one test probe toward a structure in a semiconductor wafer to retest it. Deceleration of the at least one test probe is detected with at least one tool for measuring and controlling deceleration of the at least one test probe as it approaches a surface of a structure in the semiconductor wafer.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.